This brief proposes a new model of inverse discrete cosine transform (IDCT) kernel for high efficiency video coding (HEVC). The kernel supports IDCT of order 4, 8, 16, and 32. The proposed architecture uses the Chen's algorithm as well as Walsh-Hadamard transform-based matrix decomposition method for complexity reduction. Additionally, an approximation scheme is proposed to replace all the coefficients by dyadic fractions on the basis of orthogonality and normality errors. As a consequence, the entire transform can be realized by using add and shift operations and hence, rotation unit is inessential. This reduces hardware cost significantly and the speed of the architecture also gets enhanced. The proposed approximated model complies with the requirements of HEVC and during video coding, less than 0.5 dB PSNR variation is observed as compared to that of the HEVC reference software. The proposed integer IDCT architecture is implemented on CMOS 90-nm ASIC platform. It is observed that it requires 36.6K logic gates at 200 MHz operating frequency.