This brief proposes a coarse-grained reconfigurable cryptographic processor for high-throughput secure network processing and cloud computing, which can implement all the commonly used symmetric and hash cryptographic algorithms. To efficiently utilize the enormous computing resource on reconfigurable computing fabrics, a configuration acceleration system is designed for scheduling. A multi-channel storage network is presented to improve the efficiency of reading/loading data. The proposed reconfigurable processor is fabricated on a 9.91 mm² silicon by using 65-nm CMOS technology with 500-MHz frequency. Under 60 Gb/s throughput, the power is still controlled within 1 Watt (e.g., AES 64 Gb/s/0.625 W). The energy efficiency (throughput/power) is 5.2× ~ 149.6× larger than that of the state-of-the-art designs.