This brief presents an 8 GSps 14 bit current steering RF digital-to-analog converter (DAC) for communication system. Double edge sampling method is adopted to reduce maximum clock frequency. To suppress the third-order intermodulation (IM3), current switch driver with enhanced reset circuit is proposed. An improved dynamic element matching (DEM) method based on optimized switching sequence is adopted. According to experimental result, the measured IM3 is below -62 dBc up to 3.6 GHz. The digital interpolation and up-converters block are included. Eight lane 10 Gb/s JESD 204B receiver are integrated. The chip is fabricated in 40-nm CMOS, with a die size of 2.75 × 3 mm².