Integration of high frequency buck regulators with digital logic in the same die is becoming a standard for next generation processor power delivery. The input voltage of these regulators exceed well beyond the maximum voltage rating of the digital transistors. The voltage swing of the power FETs in a traditional cascoded power stage scales proportionally with the input voltage. In this brief, we propose a novel driving scheme for maintaining a constant overdrive across the power FETs in a cascoded power stage, all implemented in low-voltage digital devices. A 130nm CMOS test-chip with 25nH inductance and 33MHz switching frequency achieves a peak power-stage efficiency of 80.1% and improves the power efficiency by 5% compared to a traditional driving scheme of V_IN/2 overdrive.