This brief presents a high power supply ripple rejection (PSRR) and low line sensitivity voltage reference for driving right leg (DgRL) circuits in bio-potential signals readout systems. The proposed voltage reference circuit employs the collector common-mode voltage extraction feedback (CVEF) architecture and the all-sub-threshold-region low line sensitivity (ASLS) circuit to achieve high PSRR and low line sensitivity. A prototype has been taped out using a 0.35- $\mu \text{m}$ CMOS technology, and the chip core occupies 0.16 mm². The measured reference voltage is about 1.22 V, and its average temperature coefficient (TC) in the range of −40 °C to 125 °C is 12.3 ppm/°C. The measured PSRR of a random chip with 5 V supply voltage is −80.29 dB, −80.16 dB, −82.46 dB, −76.04 dB, −73.17 dB and −38.59 dB at 10 Hz, 50 Hz, 100 Hz, 500 Hz, 1 kHz and 100 kHz, respectively. In the 2–5 V $V_{DD}$ range, the line sensitivity of the proposed circuit is 0.018 %/V. The current consumption of the whole circuit is 23.2 $\mu \text{A}$ when $V_{DD}$ takes the minimum value 2 V at room temperature.