High-radix Montgomery Modular Multiplication (MMM) is flexible and consumes fewer cycles, but turns inefficient especially when it comes to low-bit calculation. In this brief, we propose a high-radix MMM algorithm, called Separated Iterative Digit-Digit Modular Multiplication (S-IDDMM), which accelerates the MMM by taking full advantage of multipliers and adders. The relationship among clock cycles, pipeline of multiplications and number of multipliers for the proposed algorithm is derived and utilized to optimize the overall efficiency jointly. Xilinx Virtex-7 FPGA implementations of S-IDDMM in 256 bits and 512 bits are constructed with radix-32 and radix-64, respectively. Compared with IDDMM design reported elsewhere (Amiet et al., 2016), our calculation time is reduced by more than 2 times with a similar area cost, due to deep use of multipliers and higher frequency.