In this brief we propose a completely novel approach to design robust analog circuits made up only of digital CMOS gates taken from conventional standard-cell libraries. The approach exploits the topology of CMOS NOT, NOR and NAND gates to derive a basic building block, namely basic amplifier ( $BA$ ) cell, which is equivalent to a CMOS inverter (used as a transconductance amplifier) with an additional input which allows to accurately set its static output voltage and to obtain a balanced input-output voltage transfer characteristic. We propose also a standard-cell-based control loop based on a replica bias technique which, despite PVT variations, allows to guarantee a static output voltage equal to half the supply voltage for all the $BA$ cells used in the analog section of the chip. The approach has been validated through parametric and corner simulations referring to a 130 nm CMOS process and the performed analyses have highlighted that the proposed BA cell attains reliable performance under PVT variations, whereas the conventional inverter gate taken from the standard-cell library performs in a very unreliable way in the same PVT conditions.