Mismatch of the digital-to-analog converter (DAC) elements is the major limitation for Signal to Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR) in multi-bit Delta Sigma Modulators (DSM). In this brief we extend a previously introduced technique to build an intrinsically linear 13 level DAC. An exemplary Switched-Capacitor (SC) 13-levels 20 kHz discrete-time DSM employing this technique is simulated and achieves an SFDR higher than 100 dBc on circuit level in presence of considerable capacitor mismatch. The presented DAC architecture is not limited to be used in a discrete-time modulator, but could also be employed in a Continuous-Time DSM (CTDSM).