This brief presents a 30–36 GHz CMOS power amplifier (PA) with a diode-connected analog linearizer dedicated to improving the output power and power-added efficiency (PAE) at 1-dB output compression point (OP1dB). The proposed analog linearizer performs a gain expansion, simultaneously introducing little phase distortion. In addition, a design procedure of the matching network between the analog linearizer and PA is analyzed to mitigate the impact of impedance variation caused by the control voltage and input power. As a proof of concept, the circuit is fabricated in a 65-nm CMOS process with a 0.31 mm2 total area. Measured output power and PAE at OP1dB are >13.4 dBm and >12.4%, where maximum improvement of 2.2 dB and 5.9% is achieved at 31 GHz when the analog linearizer is active. The saturated output power of >16.2 dBm is obtained with the saturated PAE of >21%. Applying a single carrier 256-QAM signal with a bandwidth of 400 MHz and a peak-to-average power ratio (PAPR) of 10.4 dB, the PA with the proposed analog linearizer can achieve the adjacent channel power ratio (ACPR) of −34 dBc at the output power of 6 dBm.