This brief proposes an efficient structure for electroencephalogram (EEG) signal recording. A single-sample strategy is proposed to mitigate metastability issues in Voltage-Controlled Oscillator (VCO) Analog Front Ends (AFEs), offering timing margins of 14 phase cycles and simplifying the result arbitration logic to 1-bit multiplexing. Additionally, an analysis of existing EEG sub-band filter designs is presented, followed by an efficient band multiplexing serial multiplier structure that capitalizes on timing slacks. This design features a reduction in both the number of multipliers and the complexity of the multiplexing network. The proposed design was implemented using 40nm CMOS technology. The VCO-AFE demonstrates stable, error-free recordings with an input-referred noise (IRN) of $0.66\boldsymbol {\mu }$ V $\boldsymbol {_{rms}}$ within 0.5–60Hz, according to the measurement results. The proposed sub-band filter exhibits substantial savings of 11% and 51% in area and power, respectively, compared to prior work when scaled to the same technology node.