This brief presents a balanced power amplifier (BPA) with adaptive-bias for 5G applications based on 28-nm bulk CMOS process. The PA utilizes a differential balanced structure which cancels out reflected signals at the isolation ports, thereby improving return losses. A folded differential quadrature coupler is designed to connect respectively to the input and output of the PAs. The folded layout effectively reduces the chip size. In addition, a complementary adaptive bias is implemented to cancel out the nonlinear effects of the two PAs, significantly enhancing the overall linearity. The measure PA realizes a 3-dB bandwidth of $21.3\sim 28$ .4 GHz with a peak gain of 21.1 dB. The large-signal measurement results show that the PA achieve an OP1dB of 20.3 dBm, a $P_{\mathrm { sat}}$ of 21.6 dBm, and a peak PAE (PAEmax) of 30.9%. The measured |AM-PM|P1dB is less than 8.9°, which is $3\sim 8^{\circ }$ lower than when using a normal bias. For 5G NR FR2 200-MHz 64QAM signals, the measured $P_{\mathrm { avg}}$ / ${\mathrm { PAE}}_{\mathrm { avg}}$ / ACPR of 11.2 dBm / 6% / –24.9 dBc are achieved at the EVM of –25 dB. The DC power supply voltage is 1.8 V. The core chip size is only 0.27 mm2, demonstrating a compact design within a balanced architecture.