Neuromorphic processors are promising candidates for energy-constrained intelligent systems, as they emulate cortical computations via spatiotemporally sparse binary spikes. However, achieving high-accuracy, high-throughput and cost-efficient neuromorphic processing remains challenging. To fully utilize hardware resources for performance improvement, we propose a multi-core neuromorphic architecture characteristic of a uniform neuron-core mapping scheme and a layer-wise event-batch-based parallel processing paradigm. These techniques ensure highly balanced cross-core workloads regardless of actual mapped neural network topologies as well as unpredictable input and internally generated spike counts varying from sample to sample. An FPGA prototype of our neuromorphic processor was implemented. It exhibited comparably high on-chip learning accuracies on various visual and non-visual benchmarks, high learning/inference frame rates (low processing latencies), with a moderate amount of logic and memory resource consumptions.