Discrete Cosine Transform (DCT) is a commonly used building block for image and video compression. In this article, we present a Markov Random Field (MRF)-based design for DCT implementation because MRF logic gates outperform standard non-MRF units by achieving high noise immunity for applications to logic-based computing systems in deep sub-micron condition. Furthermore, it is found that stochastic logic, a low-cost form of number representation, can also efficiently simplify computations. By combining these two techniques, we present an improved DCT hardware circuit. The example eight-point one-dimensional DCT (1D DCT) system is simulated using 65 nm CMOS technology. Simulation results show that the proposed MRF design can achieve 13% higher noise immunity and 47% area saving, compared with the typical stochastic 1D DCT using classical Master-and-Slave architecture. While achieving the same error rate of 0.21, power consumption is reduced by 52%.