Combining ATPG and symbolic simulation for efficient validation of embedded array systems | IEEE Conference Publication | IEEE Xplore

Combining ATPG and symbolic simulation for efficient validation of embedded array systems


Abstract:

In the past, symbolic trajectory evaluation (STE) has been shown to be effective for verifying individual array blocks. However, when applying STE to verify multiple arra...Show More

Abstract:

In the past, symbolic trajectory evaluation (STE) has been shown to be effective for verifying individual array blocks. However, when applying STE to verify multiple array blocks together as a single system, the run-time OBDD (ordered boolean decision diagrams) sizes would often blow up. In this paper, we propose the use of both an ATPG-based justification engine and symbolic simulation to facilitate the application of STE proof methodology for array systems. Our method translates a given verification problem instance into ATPG justification objectives, and partitions a given design into ATPG and symbolic simulation domains. Then, by developing a scheme that enables the ATPG justification engine to work closely with the symbolic simulator, the runtime OBDD sizes during each symbolic simulation run can be limited. We demonstrate the effectiveness of our approach by verifying the memory management units (MMU) in Motorola high-performance microprocessors. The verification of a MMU as a whole was not possible before because of the OBDD size blow-up problem when symbolic simulation is used in the STE proof process.
Date of Conference: 10-10 October 2002
Date Added to IEEE Xplore: 10 December 2002
Print ISBN:0-7803-7542-4
Print ISSN: 1089-3539
Conference Location: Baltimore, MD, USA

References

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