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Embedded memory test and repair: infrastructure IP for SOC yield | IEEE Conference Publication | IEEE Xplore

Embedded memory test and repair: infrastructure IP for SOC yield

Publisher: IEEE

Abstract:

Today's system-on-chip typically embeds memory IP cores with very large aggregate bit count per SoC. This trend requires using dedicated resources to increase memory yiel...View more

Abstract:

Today's system-on-chip typically embeds memory IP cores with very large aggregate bit count per SoC. This trend requires using dedicated resources to increase memory yield, while containing test and repair cost and minimizing time-to-volume. This paper summarizes the evolution of such yield optimization resources, compares their trade-offs, and concentrates on on-chip infrastructure IP. To maximize the repair efficiency, this infrastructure IP needs to leverage the memory design knowledge and the process failure data. The ideal solution is to integrate the memory IP and its infrastructure IP into a single composite IP that yields itself effectively.
Date of Conference: 10-10 October 2002
Date Added to IEEE Xplore: 10 December 2002
Print ISBN:0-7803-7542-4
Print ISSN: 1089-3539
Publisher: IEEE
Conference Location: Baltimore, MD, USA

References

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