Cost-effective approach for reducing soft error failure rate in logic circuits | IEEE Conference Publication | IEEE Xplore
Skip to Main Content
IEEE.org
IEEE
Xplore
IEEE SA
IEEE Spectrum
More Sites
Subscribe
Donate
Cart
Create Account
Personal Sign In
Browse
My Settings
Help
Institutional Sign In
Institutional Sign In
All
Books
Conferences
Courses
Journals & Magazines
Standards
Authors
Citations
ADVANCED SEARCH
Conferences
>
International Test Conference...
Cost-effective approach for reducing soft error failure rate in logic circuits
Publisher:
IEEE
Cite This
PDF
K. Mohanram
;
N.A. Touba
All Authors
Sign In
or Purchase
181
Cites in
Papers
3
Cites in
Patents
645
Full
Text Views
Alerts
Alerts
Manage Content Alerts
Add to Citation Alerts
Abstract
Authors
Figures
References
Citations
Keywords
Metrics
More Like This
Download PDF
Download References
Request Permissions
Save to
Alerts
Metadata
First Page of the Article
Published in:
International Test Conference, 2003. Proceedings. ITC 2003.
Date of Conference:
30 September 2003 - 02 October 2003
Date Added to IEEE
Xplore
:
08 March 2004
Print ISBN:
0-7803-8106-8
Print ISSN:
1089-3539
DOI:
10.1109/TEST.2003.1271075
Publisher:
IEEE
Conference Location:
Charlotte, NC, USA
First Page of the Article
Hide First Page Preview
Contents
Authors
Figures
References
Citations
Keywords
Metrics
References
References is not available for this document.