Abstract:
The characteristics defining non-determinism for PCI Express busses are explored. The RapidIO/sup /spl reg// bus is used as a point of comparison. ATE architecture is pro...Show MoreMetadata
Abstract:
The characteristics defining non-determinism for PCI Express busses are explored. The RapidIO/sup /spl reg// bus is used as a point of comparison. ATE architecture is proposed to significantly reduce the yield and throughput impact of random output. A specific architecture is explored and proposed for real-time pass/fail analysis of HSS data streams in the ATE environment.
Published in: 2004 International Conferce on Test
Date of Conference: 26-28 October 2004
Date Added to IEEE Xplore: 31 January 2005
Print ISBN:0-7803-8580-2