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Design for testability features of the SUN microsystems niagara2 CMP/CMT SPARC chip | IEEE Conference Publication | IEEE Xplore

Design for testability features of the SUN microsystems niagara2 CMP/CMT SPARC chip


Abstract:

The Niagara2 System-on-Chip is SUN Microsystem’s latest processor in the Eco-sensitive CoolThreads line of multi-threaded servers. This DFT survey of the Niagara2 chip in...Show More

Abstract:

The Niagara2 System-on-Chip is SUN Microsystem’s latest processor in the Eco-sensitive CoolThreads line of multi-threaded servers. This DFT survey of the Niagara2 chip introduces the RAWWCas memory test, a Hybrid Flop Design and a fast efficient bitmapping architecture called DMO. It also showcases some excellent DFT results for this challenging system- on-chip design project.
Date of Conference: 21-26 October 2007
Date Added to IEEE Xplore: 22 January 2008
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Conference Location: Santa Clara, CA, USA

References

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