Abstract:
The paper presents a preemptive test application scheme for system-on-chip (SoC) designs with EDT-based compression. It seamlessly combines a new test data reduction tech...Show MoreMetadata
Abstract:
The paper presents a preemptive test application scheme for system-on-chip (SoC) designs with EDT-based compression. It seamlessly combines a new test data reduction technique with a test scheduling algorithm and a novel test access mechanism. It is particularly well suited for SoC devices comprising non-isolated cores, i.e., blocks that occasionally need to be tested simultaneously.
Published in: 2010 IEEE International Test Conference
Date of Conference: 02-04 November 2010
Date Added to IEEE Xplore: 20 January 2011
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