Low capture power at-speed test in EDT environment | IEEE Conference Publication | IEEE Xplore

Low capture power at-speed test in EDT environment


Abstract:

This paper presents a novel low capture power test scheme integrated with EDT (Embedded Deterministic Test) environment. The key contribution of this paper is to generate...Show More

Abstract:

This paper presents a novel low capture power test scheme integrated with EDT (Embedded Deterministic Test) environment. The key contribution of this paper is to generate test vectors that in capture mode mimic functional operation from switching activity point of view. Experimental results presented for industrial circuits demonstrate the effectiveness of the proposed method.
Date of Conference: 02-04 November 2010
Date Added to IEEE Xplore: 20 January 2011
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Conference Location: Austin, TX, USA

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