Abstract:
High volume testing of complex System on Chip (SoC) designs at reasonable test cost requires high test data and test time compression. We present a multilevel scan compre...Show MoreMetadata
Abstract:
High volume testing of complex System on Chip (SoC) designs at reasonable test cost requires high test data and test time compression. We present a multilevel scan compression architecture that combines a flexible test compression core with an efficient dynamic broadcast structure and a high speed data access technique. Full X-tolerance, power-aware scan shift and diagnosis are supported through the entire architecture. We present a flow for assembling the various components that limits the impact on area and timing by minimizing test signals and improving modularity of the inserted design-for-test (DFT) structures. These techniques provided a reduction of 600x in test data volume and over 2300x in test time on large Graphics Processor Units (GPU) designs.
Published in: 2014 International Test Conference
Date of Conference: 20-23 October 2014
Date Added to IEEE Xplore: 09 February 2015
Electronic ISBN:978-1-4799-4722-5