Low-area energy-efficient security primitives are key building blocks for enabling end-to-end content protection, user authentication and data security in IoT platforms. This talk describes the design of security circuit primitives that employ energy-efficient circuit techniques with optimal hardware-friendly arithmetic for seamless integration into area/battery-constrained IoT systems: 1) A 2040-gate AES accelerator achieving 289-Gbps/W efficiency in 22-nm CMOS, 2) Hardened hybrid physically unclonablef Function (PUF) circuit to generate a 100% stable encryption key. 3) All-digital TRNG to achieve >0.99-min-entropy with 3-pJ/bit energy efficiency. The talk will also discuss design issues related to side-channel leakage of key information, and how they may be addressed during design of encryption circuits. Finally, the talk will touch upon existing challenges of maintaining the integrity of security circuits, while still enabling testability and post-silicon validation.