The number of on-chip embedded instruments required for testing, debugging, and monitoring integrated circuits (ICs) has increased dramatically. The IEEE 1687 (IJTAG) standard can allow efficient access to these embedded instruments by dynamically reconfiguring the scan chain using Segment Insertion Bits (SIBs). Unfortunately, instruments that require a large amount of test data and several accesses during test mode still result in long test times when the test data is shifted through the scan path serially. To provide high bandwidth access to the embedded instruments, we describe a SIB-based Parallel-IJTAG network architecture that can significantly reduce test times. The SIB programming access time overhead is equal to that of the corresponding serial network. Different ways of implementing Parallel-SIBs (P-SIBs) and the security implications of a Parallel-IJTAG network are explored. We show that despite the increased bandwidth of the scan path, the security provided by Locking SIBs can be maintained in a parallel network. For example, the expected amount of time for successful random brute force attacks on Locking Parallel SIBs of sufficient key sizes is over 12,000 years.