This paper presents a methodology for reducing functional test time in subthreshold SoCs targeting ultra-low power (ULP) internet-of-things (IoT) devices. Due to their low operating speed and voltage, subthreshold SoCs require significantly longer time to test than traditional SoCs. The proposed method models trans-threshold correlations to allow high voltage, high speed testing while accurately predicting delay and power at the low, subthreshold operational voltage. This approach is orthogonal to other traditional testing methodologies and can significantly reduce the test time of digital and memory blocks on subthreshold SoCs. Using this process results in 5.4 × savings in test time for sequential and combinational test circuits, and over 2 × savings in test time for memory circuits with no overhead to area or prefabrication design time.