Fast yield ramping in a new technology to meet aggressive time-to-market deadlines requires a comprehensive design and fabrication methodology for silicon test structures that systematically explores and validates the technology. Prior work proposed a novel logic characterization vehicle (LCV), along with an implementation flow that produces a test chip that ensures logic demographics that resemble real products, and ensures near-optimal testability and diagnosability. This work describes a design flow that efficiently incorporates FEOL layout properties into an easily testable and diagnosable logic-based test chip. Experiments comparing testability, logic and layout properties between the test chip design and various benchmark circuits demonstrate the efficacy of this approach.