Scan shift power consumption is one of the major concerns in low power circuits. While there are multiple design for testability (DFT) techniques proposed in the literature for addressing both peak and average shift power optimization, most of the solutions impose additional design overhead which may impact functional performance of the device. In this paper, we propose a novel frequency scaled segmented scan architecture which adopts a custom test method based on scan shift frequency scaling and shifting of scan data using multi-phase clock latching mechanism. Unlike the conventional segmented scan based methods, the proposed solution is non-intrusive to functional mode of operation and it significantly helps alleviate the impact of both peak and average shift power on large designs without any impact to overall test-application time. Alternatively, the proposed method can also be used to enable faster test-application time to optimize the overall test-time and test cost without any impact on scan shift power consumed. The various implementation/integration aspects of the proposed method are discussed in the context of a 45nm low power SoC, along with various experimental and silicon results.