Abstract:
This paper discusses a new architecture for the PWM generation in digital control hardware intended for control of three-phase power converters. The novelty of the propos...Show MoreMetadata
Abstract:
This paper discusses a new architecture for the PWM generation in digital control hardware intended for control of three-phase power converters. The novelty of the proposed architecture is based on the use of emerging flash memory devices. An infinite number of state combinations and sequences is therefore available during a sampling interval. Three optimization criteria are herein simultaneously employed, dealing with optimal sharing of the zero sequence states, variation of the pulse frequency, and over-modulation through an optimal pattern. Performance is measured with the harmonic current factor and this is demonstrated to surpass the results of conventional implementation. The proposed architecture is versatile because it can be used at different sampling and fundamental frequencies, different operation modes, and without jeopardizing transient performance. While the current products allow implementation on external 64-MB flash memory, this architecture can be adopted in the future within the next-generation microcontrollers.
Published in: IEEE Transactions on Industrial Informatics ( Volume: 8, Issue: 3, August 2012)