This paper proposes a leading-subcycles capacitor error-averaging (LCEA) scheme to reduce the capacitor mismatch error of cyclic analog-to-digital converters (ADCs) while only slightly lowering the conversion rate. The scheme does not need complicated structures or extra calibration circuits. Hence, the proposed LCEA scheme can be used for cyclic ADCs to achieve high accuracy while maintaining their low-power and small-area features. In addition, the figure of merit (FOM) versus the number of averaging operations in a complete conversion cycle is analyzed such that power-accuracy-speed tradeoffs can be optimized. A proof of concept 12-bit cyclic ADC is implemented to compare the performance of the proposed LCEA scheme with that of a conventional cyclic ADC. The chip is fabricated in a 3.3-V, 0.35-μm CMOS process. Measurements demonstrate that the cyclic ADC with only two averaging operations has a 6 dB and 10 dB higher signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR), respectively, than the conventional cyclic ADC, and with only a slightly reduced conversion rate of 12/13 times than that of the conventional cyclic ADC. In addition, the measured FOM is greatly reduced to 0.55 times of that obtained using the conventional scheme which indicates the advantage of the LCEA technique.