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Low-Power Die-Level Process Variation and Temperature Monitors for Yield Analysis and Optimization in Deep-Submicron CMOS | IEEE Journals & Magazine | IEEE Xplore

Low-Power Die-Level Process Variation and Temperature Monitors for Yield Analysis and Optimization in Deep-Submicron CMOS


Abstract:

This paper reports design, efficiency, and measurement results of the process variation and temperature monitors for yield analysis and enhancement in deep-submicron CMOS...Show More

Abstract:

This paper reports design, efficiency, and measurement results of the process variation and temperature monitors for yield analysis and enhancement in deep-submicron CMOS circuits. Additionally, to guide the verification process with the information obtained through monitoring, two efficient algorithms based on an expectation-maximization method and adjusted support vector machine classifier are proposed. The monitors and algorithms are evaluated on a prototype 12-bit analog-to-digital converter fabricated in standard single poly six-metal 90-nm CMOS.
Published in: IEEE Transactions on Instrumentation and Measurement ( Volume: 61, Issue: 8, August 2012)
Page(s): 2212 - 2221
Date of Publication: 06 February 2012

ISSN Information:


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