This brief presents a foreground calibration method for correcting linear and memoryless errors in multibit stage pipelined A/D converters (ADCs). Using a least-squares minimization, the method extends the radix-based pipelined ADC calibration to multibit stage architectures by adopting one-of- n encoding with a radix vector expansion, thereby correcting both nonideal stage gain and random code-boundary transitions in a globally optimal sense. Numerical experiments via Monte Carlo simulation of 400 ADCs show that the proposed calibration method can improve the effective number of bits from 9.5 b to 14.4 b for a hypothetical 15-b 200-MS/s pipelined ADC design in 90-nm CMOS process.