For the measurement of text high-speed communication signals, whether it is to check the signal’s bit error rate (BER) with a BER tester or to record the signal’s eye diagram with an equivalent-time oscilloscope, a clock and data recovery (CDR) circuit is required to generate a trigger signal properly aligned to the input data signal. For the system under test, where multiple communication protocols coexist, a wide operation frequency range and low-jitter CDR circuit can undoubtedly improve the measurement efficiency and reduce the cost. However, obtaining broad frequency coverage and minimal recovery clock jitter simultaneously has always been a challenge in the design of CDR circuits. This article proposes a CDR circuit combining a multiband LC-voltage-controlled oscillator (VCO) and a configurable frequency divider, which effectively expands the operating frequency range of the CDR while maintaining the low jitter of the recovered clock. A 0.2–7.1-Gb/s CDR circuits with a 1.9-ps rms jitter of the recovered clock under a 7.1-Gb/s input pseudorandom binary sequence (PRBS) signal is implemented in 65-nm CMOS. Compared with other LC-VCO-based CDRs, the proposed CDR achieves better energy efficiency and lower jitter performance.