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Design of Clocked Comparator Preventing Bit Errors to Improve Reliability of Low-Speed DRAM Measurement | IEEE Journals & Magazine | IEEE Xplore

Design of Clocked Comparator Preventing Bit Errors to Improve Reliability of Low-Speed DRAM Measurement


Abstract:

For manufacturing a dynamic random access memory (DRAM), a low-speed wafer test is required to identify cell and circuit defects and repair them. A clocked comparator in ...Show More

Abstract:

For manufacturing a dynamic random access memory (DRAM), a low-speed wafer test is required to identify cell and circuit defects and repair them. A clocked comparator in the data transfer path samples an entered low-speed test data pattern. However, leakage current can cause a sampling error, resulting in inaccurate test results; this degrades the testing reliability. To mitigate this issue, we present strongARM latch- and dynamic amplifier-based clocked comparators that can prevent bit errors. A prototype chip was fabricated using the 28-nm CMOS process, and the measurement was performed using five prototypes with the TT process corner at room temperature. The bit-flipping error compensation was proved at operating speeds of 0.1–16 MHz for 1.0, 1.3, 1.4, and 1.8-V supply voltages.
Article Sequence Number: 3532410
Date of Publication: 25 September 2023

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