Parallelism has become one of the key architectural features in 40-/100-/400-Gb Ethernet multi lane distribution (MLD) standards. The MLD packetizes and distributes traffic adaptively over parallel lanes and maps them to parallel network interfaces for wide area transmission, typically over optical networks. As such, the MLD creates not only new network topology abstractions but also enables modular implementations of various new features to improve the system performance. In this paper, we study the performance of the parallelized Ethernet in combination with erasure coding and more specifically random linear network coding (RLNC). We present a novel theoretical modeling framework, including the derivation of upper and lower bounds of differential delay and the resulting receiver queue size-a critical performance measure in the high-speed Ethernet. The results show benefits of a combined usage of parallelism and RLNC: with a proper set of design parameters, the differential delay and the receiver buffer size can be reduced significantly, while cross-layer design and path computation greatly simplified.