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CHiP: A Configurable Hybrid Parallel Covering Array Constructor | IEEE Journals & Magazine | IEEE Xplore

CHiP: A Configurable Hybrid Parallel Covering Array Constructor


Abstract:

We present a configurable, hybrid, and parallel covering array constructor, called CHiP. CHiP is parallel in that it utilizes vast amount of parallelism provided by graph...Show More

Abstract:

We present a configurable, hybrid, and parallel covering array constructor, called CHiP. CHiP is parallel in that it utilizes vast amount of parallelism provided by graphics processing units (GPUs). CHiP is hybrid in that it bundles the bests of two construction approaches for computing covering arrays; a metaheuristic search-based approach for efficiently covering a large portion of the required combinations and a constraint satisfaction-based approach for effectively covering the remaining hard-to-cover-by-chance combinations. CHiP is configurable in that a trade-off between covering array sizes and construction times can be made. We have conducted a series of experiments, in which we compared the efficiency and effectiveness of CHiP to those of a number of existing constructors by using both full factorial designs and well-known benchmarks. In these experiments, we report new upper bounds on covering array sizes, demonstrating the effectiveness of CHiP, and the first results for a higher coverage strength, demonstrating the scalability of CHiP.
Published in: IEEE Transactions on Software Engineering ( Volume: 45, Issue: 12, 01 December 2019)
Page(s): 1270 - 1291
Date of Publication: 17 May 2018

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