Recently, various specialized Software Defined Radio (SDR) baseband processors have been proposed for meeting the high performance and programmability requirements for emerging wireless communication applications. In order to support high throughput wireless communication, the SDR baseband processors typically employ many parallel computation elements, which may also be used for performing other signal processing applications. This paper explores the feasibility of performing complex media processing on such SDR baseband processors. Specifically, the full HD 1080p state-of-the-art H.264/AVC media decoding has been implemented onto a recent version of the ADRES based SDR baseband processor. Since the processor was originally designed exclusively for wireless baseband applications, algorithm and architecture co-optimizations are required to make the goal feasible. Following algorithm analysis, the computationally dominant tasks of the H.264/AVC, including the motion compensation, the intra prediction, the inverse integer transform, and the deblocking filter, have been selected to be mapped onto the ADRES. The experimental results show that, with limited architectural extensions, the ADRES based baseband processor achieves competitive performance efficiency, even compared with several processors that are specifically optimized for the media decoding application.