Abstract:
This paper describes a 9-bit Successive Approximation Register Analog to Digital Converter (SAR-ADC) design in CMOS technology, particularly I4T, 0.35 μm, 45 V, used in a...Show MoreMetadata
Abstract:
This paper describes a 9-bit Successive Approximation Register Analog to Digital Converter (SAR-ADC) design in CMOS technology, particularly I4T, 0.35 μm, 45 V, used in automotive industry for sensor application. There are the individual analogue components of the SAR-DAC described in this paper: the Comparator, the R-2R Digital to Analog Converter (DAC) and the Operational Amplifier (OPA). The functionality and the parameters of the SAR-ADC were verified in analog design environment Cadence Virtuoso. The parameters of the designed SAR-ADC are published in this paper.
Date of Conference: 05-07 July 2017
Date Added to IEEE Xplore: 23 October 2017
ISBN Information: