This paper connects the linear steady-state systematic error models of the time- and frequency-interleaved analog-to-digital converters (ADCs). Exposing their relations is of importance because estimation and compensation methods developed for one architecture may therefore apply to the other. Most critical impairments in both ADC structures include static mismatches and random jitter. The former has been well studied and can be generalized to the model connection, whereas not much is known regarding the latter. To support designers becoming more capable of making optimal design and architectural decisions on parallel ADCs, comprehensive phase noise analysis and comparison are carried out to reveal the distinctions between these two sampling architectures. Design examples with considerations are also provided for demonstration purposes.