PAElib 2.0: Power&Area Aware Modeling of CMOS Digital Circuits in VHDL | IEEE Conference Publication | IEEE Xplore

PAElib 2.0: Power&Area Aware Modeling of CMOS Digital Circuits in VHDL


Abstract:

This paper presents the power&area aware modeling approach of CMOS digital circuits and PAELib, its VHDL implementation. Today's low-power and high power density designs ...Show More

Abstract:

This paper presents the power&area aware modeling approach of CMOS digital circuits and PAELib, its VHDL implementation. Today's low-power and high power density designs justify the necessity of power and area estimates in early digital design stage, as behavioral or register transfer level description. The power&area aware modeling complements a functional (or behavioral) description with power and area estimation features. A solution for this modeling was presented previously by the authors in an earlier version of PAELib. The initial implementation of this library lacked the possibility to estimate the power&area consumption of functional descriptions, only structural description at the gate level were suited for estimation. The new version of the library allows the user first to synthesize a circuit and map it in a target technology, then estimate its power & area requirements using an event driven circuit simulator, finally create a power&area aware model.
Date of Conference: 07-09 July 2020
Date Added to IEEE Xplore: 11 August 2020
ISBN Information:
Conference Location: Milan, Italy

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