In this paper, we present a fast and accurate thermal aware analytical placer. A thermal model is constructed based on a Green function with discrete cosine transform (DCT) to generate full chip temperature profile. Our thermal model is tightly integrated with an analytical placer implemented based on the SimPL framework. A temperature spreading force based on the Gaussian model is proposed to reduce the maximum on-chip temperature and optimize tradeoff between total half-perimeter wirelength and on-chip maximum temperature. The temperature profile generated using our thermal model is verified by the ANSYS ICEPAK and obtains an average deviation within 3.0% with 240× speedup.