When the conventional method of defining sequential element timing parameters is used in conjunction with the conventional method of accounting for clock uncertainty in timing analysis, the results are overly pessimistic because, when clock uncertainty is nonzero, the element can never be simultaneously critical for both setup time and clock-toQ. This brief shows that the actual sequencing overhead of conventional flip-flops is 0.5-1 fanout-of-4 (FO4) inverter delay shorter than conventional models predict. High-performance flip-flops, with a modest transparency window, can be 2 FO4 delays faster. While the exact overhead becomes a function of the clock uncertainty, for typical uncertainties, the timing parameters are well-approximated using minimum setup and clock-toQ values.