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Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology | IEEE Journals & Magazine | IEEE Xplore

Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology


Abstract:

This brief presents a double-node-upset-resilient latch (DNURL) design in 22-nm CMOS technology. The latch comprises three interlocked single-node-upset-resilient cells a...Show More

Abstract:

This brief presents a double-node-upset-resilient latch (DNURL) design in 22-nm CMOS technology. The latch comprises three interlocked single-node-upset-resilient cells and each of the cells mainly consists of three mutually feeding back Muller C-elements. Simulation results demonstrate the double-node upset resilience and a 73.0% delay-power-area product saving on average compared with the up-to-date DNURL designs.
Page(s): 1978 - 1982
Date of Publication: 13 February 2017

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