Abstract:
This paper presents an automatic resistive random access memory (ReRAM) SPICE model generator, which enables fast ReRAM circuit evaluation with standard SPICE. Our model ...Show MoreMetadata
Abstract:
This paper presents an automatic resistive random access memory (ReRAM) SPICE model generator, which enables fast ReRAM circuit evaluation with standard SPICE. Our model generator automatically produces SPICE models of ReRAM devices and selectors from the measured I-V data to reduce too much time consumption in manual model development for ReRAM devices and simulation of the target ReRAM circuits. To verify our method, SPICE models for diverse ReRAMs were automatically generated from measured data and simulated with various circuits. The results show that our model can accurately describe the original data and allows fast quantitative evaluation of ReRAM circuits. Because developing SPICE models of ReRAMs and simulating them with circuits have been the critical time-consuming procedure in ReRAM research, these results show that our method enables early ReRAM evaluation.
Published in: IEEE Transactions on Very Large Scale Integration (VLSI) Systems ( Volume: 25, Issue: 6, June 2017)