Neuromorphic utilizes VLSI technology to implement a brain-inspired architecture. Recently, a brain-inspired associative memory with large capacity and robust retrieval, known as columnar-organized memory (COM), has been introduced. COM is a combination of spiking winner-take-all (WTA) units, which is inspired by the cortex structure. In this paper, a hardware architecture of COM is proposed that is presented at three levels of design. At the level I, a low-power circuit of a leaky integrate and fire neuron is introduced that is compatible with the architecture of COM. At the level II, the assembly of the proposed neuron and a single memristor crossbar array are used to implement a WTA module. At the level III, a COM hardware architecture is developed using the combination of the WTA modules and memristor crossbar arrays. The ex situ method is utilized to train the COM hardware. The simulations are performed at all design levels. First, the power consumption of the neuron circuit is evaluated. It consumes 4.3 pJ/spike, and its static power is 182 pW. Second, the operation of the WTA module is deliberated. Finally, the operation of the COM hardware for message storage and retrieval is evaluated in the presence of the hardware imperfections.