Power analysis attacks have become a serious threat to security systems by enabling secret data extraction using side-channel leakage information. Embedded memories, often implemented with 6T SRAM cells, serve as a key component in many of these systems. However, conventional SRAM cells are prone to side-channel leakage power attacks. To provide resiliency to these types of attacks, we propose a symmetric 8T SRAM cell which incorporates two more transistors than the conventional 6T cell to significantly reduce the correlation between the stored data and the leakage currents. To demonstrate the improved security of the suggested memory array, both cells were implemented in a 65-nm CMOS technology. Simulation results, including Monte Carlo analysis and signal-to-noise ratio comparison, illustrate the resiliency of the 8T cell to leakage power attacks.