In this paper, we present a third-order nine-level continuous-time delta–sigma modulator, in which a capacitor-based voltage digital-to-analog converter is used to compensate for excess loop delay of up to half a clock period, with margins of ±30%. To evaluate its effectiveness, the prototype is implemented in 65-nm CMOS technology with an active area of 0.516 mm². The experimental results show a dynamic range (DR) of 82 dB, a signal-to-noise ratio of 75.8 dB, a signal-to-noise-and-distortion ratio of 72.1 dB, and a spurious-free DR of 78.8 dB at a sampling frequency of 128 MHz and a bandwidth of 2 MHz. The total power consumption is 3.8 mW from a 1.2-V supply.