Abstract:
This paper reports on an energy-efficient Δ-Σ readout IC (ROIC) with a high power-supply-rejection ratio (PSRR). The static power consumption is minimized by applying a z...Show MoreMetadata
Abstract:
This paper reports on an energy-efficient Δ-Σ readout IC (ROIC) with a high power-supply-rejection ratio (PSRR). The static power consumption is minimized by applying a zero-crossing-based (ZCB) circuit to implement switched-capacitor (SC) integrators, while the resistive sensor is embedded inside the circuit to reuse the bias current. Oversampling Δ-Σ modulation also directly provides the digitized output, avoiding the need for a power-hungry instrumentation amplifier while preserving the linear settling behavior of the ZCB SC integrators. A dual-path bridge measurement aids in upholding PSRR of ROIC against bridge imbalance. Prototyped in 0.18-μm CMOS, the dual-path ROIC for the bridge measurement shows a nonlinearity of c400 ppm and an rms-noise-equivalent resolution of 13 bits at a conversion rate of 8 kS/s, corresponding to a figure of merit of 1.05-pJ/conversion step. The achieved noise-frequencyindependent PSRR is 65 dB, and the supply and temperature sensitivities are 0.23%/V and 55 ppm/°C, respectively.
Published in: IEEE Transactions on Very Large Scale Integration (VLSI) Systems ( Volume: 27, Issue: 4, April 2019)