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A PVT-Tolerant MDLL Using a Frequency Calibrator and a Voltage Monitor | IEEE Journals & Magazine | IEEE Xplore

A PVT-Tolerant MDLL Using a Frequency Calibrator and a Voltage Monitor

Publisher: IEEE

Abstract:

In this brief, a multiplying delay-locked loop (MDLL) using a frequency calibrator (FC) and a voltage monitor (VM) is presented. This FC uses a delay-calibrated subsampli...View more

Abstract:

In this brief, a multiplying delay-locked loop (MDLL) using a frequency calibrator (FC) and a voltage monitor (VM) is presented. This FC uses a delay-calibrated subsampling phase detector (SSPD) to reduce the frequency error. The VM is used to cover a wide frequency variation. This MDLL is fabricated in 40-nm CMOS technology. Its active area is 0.013 mm 2 , and the power consumption is 5.2 mW from a supply of 1 V. It exhibits a root-mean-square jitter of 229 fs at 2.4-GHz output and the reference spur of -54.3 dBc under a reference clock of 150 MHz.
Page(s): 2698 - 2702
Date of Publication: 18 July 2019

ISSN Information:

Publisher: IEEE

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