Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-Power MCUs | IEEE Journals & Magazine | IEEE Xplore

Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-Power MCUs


Abstract:

Embedded static random access memories (SRAMs) with cost-effective test screening circuitry are demonstrated for low-power microcontroller units (MCUs). The probing test ...Show More

Abstract:

Embedded static random access memories (SRAMs) with cost-effective test screening circuitry are demonstrated for low-power microcontroller units (MCUs). The probing test step at the low temperature (LT) of -40 °C is obviated by imitating pseudo-LT (PLT) conditions in the package test, where a sample is measured at room temperature (RT). Monte Carlo simulation is carried out considering local Vt variations as well as contact soft open failure (high resistance), confirming good minimum operating voltage ( Vmin) correlation between LT and PLT conditions. Test chips with two types of 4-Mbit single-port SRAM macros and 1-Mbit dual-port SRAM macro are designed and fabricated using low-power 40-nm CMOS technology. Measurement results demonstrate that the proposed test method reproduces LT conditions and screens out LT failures with less overscreening. The proposed test method eliminates 1/3 or more of the test costs.
Page(s): 1495 - 1499
Date of Publication: 03 June 2021

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