An Area-Efficient SAR ADC With Mismatch Error Shaping Technique Achieving 102-dB SFDR 90.2-dB SNDR Over 20-kHz Bandwidth | IEEE Journals & Magazine | IEEE Xplore

An Area-Efficient SAR ADC With Mismatch Error Shaping Technique Achieving 102-dB SFDR 90.2-dB SNDR Over 20-kHz Bandwidth


Abstract:

To minimize the area of analog-to-digital converters (ADCs) for multichannel applications and break the SNDR limitation caused by DAC-induced nonlinearity, a more area-ef...Show More

Abstract:

To minimize the area of analog-to-digital converters (ADCs) for multichannel applications and break the SNDR limitation caused by DAC-induced nonlinearity, a more area-efficient mismatch error shaping (MES) scheme is proposed in noise shaping (NS) successive-approximation (SAR) ADC. By employing a switched-capacitor (SC) voltage divider, the proposed method makes the flash ADC and data weighted averaging (DWA) digital circuits in the original MES method obsolete. Therefore, the complexity of the architecture is highly reduced, and the area is significantly reduced to 0.037 mm2. In addition, the power consumption for the MES implementation is significantly decreased by more than 7.3%. The proposed SAR ADC is fabricated in GF 40-nm CMOS technology. The measurements show that the proposed MES technique improves the SFDR from 64 to 102 dB and decreases the THD from -63.6 to -95.7 dB. The SNR and SNDR in a 20-kHz bandwidth are 91.6 and 90.2 dB, respectively. The power consumption is 383.4 μW with a 1.1-V power supply at a 16-MS/s sampling rate.
Page(s): 1575 - 1585
Date of Publication: 17 June 2021

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