Power Supply Noise-Aware At-Speed Delay Fault Testing of Monolithic 3-D ICs | IEEE Journals & Magazine | IEEE Xplore

Power Supply Noise-Aware At-Speed Delay Fault Testing of Monolithic 3-D ICs


Abstract:

Monolithic 3-D (M3-D) integration is an emerging technology that offers significant power, performance, and area benefits for an integrated circuit (IC) design. However, ...Show More

Abstract:

Monolithic 3-D (M3-D) integration is an emerging technology that offers significant power, performance, and area benefits for an integrated circuit (IC) design. However, a problem with the 3-D power distribution network in such ICs is that it can lead to high power supply noise (PSN) during the capture cycles in at-speed scan testing for transition delay faults. Therefore, the failure of good chips (i.e., yield loss) resulting from the PSN-induced voltage droop is a major concern for M3-D designs. In this article, we first assess the PSN and voltage droop problems and their impact on path delays for at-speed testing of benchmark M3-D designs. Next, we present an analysis framework to identify test patterns that are most likely to lead to yield loss. We describe a test-pattern reshaping solution based on integer linear programming to make appropriate changes to the test patterns that cause yield loss. Simulation results for four M3-D benchmarks highlight the effectiveness of the proposed solution.
Page(s): 1875 - 1888
Date of Publication: 15 September 2021

ISSN Information:

Funding Agency:


References

References is not available for this document.